Three dimensional (3D) IC integration and packaging technologies enable shorter inter-chip interconnection, smaller form factor, higher packaging density, lower power consumption, and higher performance for semiconductor products. Solder bump interconnects are critical to high density chip to chip interconnection in conventional flip chip as well as 3D IC integration. Solder bump are normally deposited on contact pads on chip surfaces at the wafer level as the final wafer processing step, namely wafer bumping. After wafer bumping followed by wafer dicing, the chips (e.g. integrated circuit (IC) chips) are then flipped and positioned such that the solder bumps are aligned with matching pads of an external circuit of substrates, wafers, interposers, or another chips. Solder reflow completes the interconnection process, after which underfill material is introduced to fill the spaces between the interconnects to complete flip chip assembly.
The wafer bumping and chip assembly become more complex for 3D ICs because 3D ICs involve much thinner wafers than conventional wafers, and 3D wafers have devices and circuitry at the both sides of a wafer. The bumping and handling of thin wafers present significant challenges to manufacturing. Conventional wafer bumping requires photolithography and electroplating, which are difficult to apply when a wafer is thin due to warpage and handling. In addition, after a wafer completes the bumping process, the thermal budget of the solder bumps restricts any further wafer level processing. Therefore, it is desirable to apply bottom solder bump after the stacking of 3D ICs, which simplifies the thin wafer handling, processing, and assembly.